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AD9361 CMOS Mode

Question asked by wmaguire on Sep 10, 2014
Latest reply on Oct 12, 2016 by DragosB

Hi All,

 

First let me say I have had no issues with using the FMCOMMS2 and ZC706 reference design when the AD9361 device is interfaced using LVDS.   Unfortunately due to board layout constraints I am unable to use the device in this mode.  Consequently I need to get the device to operate in CMOS mode.  The configuration I am trying to implement is 1R1T, FDD, DDR, Dual Port as described on page 103 of the UG570 manual, sampling both TX and RX at 30.72MHz.

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The devices parallel port control registers are programmed as shown below.   The FPGA receives the 30.72MHz DATA_CLK and thats about it.  I see no TX output. 

 

The only difference as far as I can tell between this version and the LVDS version is the interface type and that the ADI reference design uses 2TX2RX configuration.  I have modified the ADI driver code to support these changes.   What is not clear is the port the TX is assigned to. On UG-570 it is set to P1_D

 

"Transmit data is driven on P1_D[11:0] by the BBP such that the setup and hold times between FB_CLK"  but the timing waveform shows it on P0_D.  I tried to change D6 of register 0x12 to swap the ports but no joy.   Please clarify if the TX data does go to P1_D in this mode.

 

I get the impression that the device is not enabled ( I see the RXFrame as "00" when it should be "10", the DDR data is all zeros and there is no output RF power) and perhaps my ENABLE and TXNRX signals might be incorrect. .  These are ignored in LVDS mode.  I assume that because the device is dual port duplex mode these signals need to be set high, so ENABLE high for reverse, TXNRX for TX?   I have also tried pulsing ENABLE and TXNRX at the start but no joy, ie

 

gpio_set_value(GPIO_ENABLE_PIN, 0);
gpio_set_value(GPIO_TXNRX_PIN, 0);
mdelay(1);
gpio_set_value(GPIO_ENABLE_PIN, 1);
gpio_set_value(GPIO_TXNRX_PIN, 1);
mdelay(1);
gpio_set_value(GPIO_ENABLE_PIN, 0);
gpio_set_value(GPIO_TXNRX_PIN, 0);

 

 

 

Unfortunately page 103 of UG570 does not mention how TXNRX is used in this mode.  It says the following about ENABLE.

 

"A pulse on the ENABLE pin (or a rising edge) triggers the beginning of data transfer, and another pulse (or falling edge) signifies the end of data transfer."  This is a little ambiguous.  Does this mean I need to toggle the ENABLE at the RX_FRAME rate?  Surely in FDD mode the transfer is continuous like LVDS mode?   Please explain and update the timing diagrams UG-570 to show the ENABLE and TXNRXN signals.   Also please note that the FMCOMMS2 no-os driver code as per the copy I am using only supports correct operation when operating in LVDS and in 2TX2RX mode.

 

Regards

 

 

Walter

 

 

 

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0x010 Parallel Configuration 1 = 0xC8 = 1100100
PP Tx Swap IQ = 1 = No spectral inversion.
PP Rx Swap IQ = 1 = No spectral inversion.
Tx Channel Swap = 0 = Setting this bit swaps the positions of Tx1 and Tx2 samples.
Rx Channel Swap = 0 = Ditto
RX Frame Pulse Mode = 1 = The AD9361 outputs an Rx frame sync signal indicating the beginning of an Rx frame. When this bit is clear, Rx frame goes high coincident with the first valid receive sample. It stays high as long as the receivers are enabled. When this bit is set, the Rx frame signal toggles with a duty cycle of 50%.

D2—2R2T Timing = 0 =
When set, the data port uses 2R2T timing, regardless of the number of enabled transmitters and receivers. When clear, the timing reflects the number of enabled signal paths.
D1—Invert Data Bus = 0 = Do not inverts the data port(s) from [11:0] to [0:11].
D0—Invert DATA CLK = 0 = Do not invert the DATA_CLK 

0x011 Parallel Port Configuration 2 = 0x00 = 00000000
D7—FDD Alt Word Order = 0 =  Valid only in full duplex, dual port, full port mode. When this bit is set, each port splits into two 6-bit halves. Rx1 uses 6 bits of a port and Rx2 uses the other 6 bits of the port (receivers are not interleaved). Tx1 and Tx2 are organized similarly.
[D6:D5]—Must be 0 = "00"
D4—Invert Tx1 = 0 =
Setting this bit digitally multiplies the Tx1 signal by −1.

 

D3Invert Tx2 = 0  = Setting this bit digitally multiplies the Tx2 signal by −1.

 

[D1:D0]—Delay Rx Data[1:0] = "00" = These bits set the delay of the Rx data relative to Rx frame, measured in ½ DATA_CLK cycles for DDR and full DATA_CLK cycles for SDR.

 


 

0x012—Parallel Port Configuration 3 = 0x02 = 00000010

 

 

D7—FDD Rx Rate = 2*Tx Rate = 0 = When clear, the Rx sample rate is equal to the Tx sample rate. When set, the Rx rate is twice the Tx rate. This bit can only be set when Bit D3 of Register 0x012 is clear (full duplex mode).

 

 

D6—Swap Ports = 0 =
Setting this bit swaps Port 0 and Port 1. Must be clear for LVDS mode.

 

 

D5—Single Data Rate = 0 = When clear, both edges of DATA_CLK are used. When set, only one edge of is used.

 

 

D4—LVDS Mode = 0 =  When clear, the data port uses single-ended CMOS. Set this bit to use LVDS. Full duplex (0x012[D3] clear), DDR (0x012[D5] clear), and dual port mode (0x012[D2] clear) are required.

 

 

D3—Half-Duplex Mode = 0 =  Clearing the bit allows simultaneous bi-directional data. Setting the bit allows data to flow in only one direction at a time. Normally, this bit equals the inverse of 0x013[D0].

 

 

D2—Single Port Mode = 0 = When clear, P0 and P1 ports are both used. When set, only one data port is used.

 

 

D1—Full Port = 1 = Used only in full duplex mode ([D3] clear) and dual port mode (D2 clear). Setting this bit forces the receivers to be on one port and the transmitters to be on the on the other port. Clearing the bit mixes receivers and transmitters on each port.

 

 

D0—Full Duplex Swap Bit = 0 =  This bit toggles between the bits used for receive data and those used for transmit data with one exception. If the FDD Alt Word Order bit (0x011[D7]) is set, then the effect is to swap the most significant 6 bits with the least significant 6 bits. It is not always valid to set this bit.


 

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