Over the last couple of weeks, I've been using the AD9279 reference design with the ML605. With the help of this forum, I've been able to almost get it working, but not quite.
I modified the design for 4 channels, and read the captured data. I take 4096 samples, so 1024 samples per channel. Plotting the data shows a nice sinusoidal (input) plot for the 4th channel, a mostly ideal plot for the 3rd, and may distortions in the 1st and 2nd. The 2nd is always the worst. All four channels have the same input. A plot is attached.
If I look at the raw data, I can see occasional spikes in the values, most often in the data corresponding to channel 2, some at channel 1, very rarely at channel 3 and never at channel 4. Switching the signals of the ADC input and the LVDS pairs in the FPGA doesn't change this, and ChipScope properly plots the output of the ADC data (hence, it is not the ADC that is causing the errors, nor the ADC capturing logic). I changed the FPGA design to send fixed patterns to the DMA, and observed that they are sometimes not read correctly in the Microblaze application (also in the same locations and with the same frequency described above). For example:
The first four should be 1010, the next four should be 0101. You can see how that sometimes fails and sometimes doesn't, and in this (usual case), it is at the second of the four "samples". I will attach the code I use to capture and read, which is essentially an adaptation of the code provided with the reference design.
Is this a problem encountered by anyone else? I'd appreciate your feedback.
I am running the ADC at fs=80Mhz or 100Mhz, with similar results. At 40Mhz, the ADC output is bad both when read from memory AND in ChipScope. This is probably a different question altogether, but I am curious why that is.