AnsweredAssumed Answered

Clock generation for AD9625 JESD204B interface

Question asked by Chris_Aed on Sep 5, 2014
Latest reply on Sep 9, 2014 by rejeesh

Hi to all,


As pointed out in an earlier thread ("Status and usage of  ad9625_fmc"), I'd like to operate the AD9625 evaluation board AD-FMCADC2-EBZ FMC together with the Virtex7 evaluation board VC707.


I've already learned from this forum that the provided AD reference design "ad9625_fmc" is still under construction (e.g. no Linux support). However, I still like to use this reference design as a blue print for my own Virtex7 JESDB interface design.


Unfortunately, the following two key blocks in the reference design seem to be AD-proprietary black boxes (only .xci files available), and I haven't found a way to look inside them to understand the design's internal clocking structure which is quiet crucial for a highspeed JESD interface.


* axi_ad9625_gt:    Xilinx GTX Transceiver IP block, modified by AD

* axi_ad9625_jsdb: Xilinx JESD204B interface IP block, modified by AD


First question:

Is there a reason to hide the most helpful information of a reference design in black boxes? Or is there a way to look inside the black boxes I have overlooked?


Second question:

I would like to use the 2.5GHz on-board oscillator of the AD-FMCADC2-EBZ as the sampling clock source. The only associated clock which is fed from the FMC board to the VC707 board is the DIVCLK which is generated by the AD9625 by dividing 2.5GHz by 4.


Thus, I'll have to derive all other clocks which are important in a JESD design from this 625MZ DIVCLK.


From my understanding of Xilinx' JEDS204B IP user guide (PG066), the only way to go is:


  • Generate a Xilinx JESD204B IP receiver where the shared logic is not in the core but in the example design (to have access to the clocking structure)
  • Use DIVCLK (625MHz) as the GTX refclk (default refclk rate would be 156.25 MHz)
  • Modify the GTX wrapper files because refclk is 625MHz and not the default value 156,25MHz
  • Add an MMCM block to derive the following clocks from the DIV clk master clock:
    • GTX RXUSRCLK = 156,25 MHz
    • JESD204B core clock = 156,25 MHz
    • JESD204B SYSREF clock (source synchronous and harmonic to all other clocks, may be 31.25MHz)


Could somebody please confirm this approach, or might there be an easier way? A short explanation how this has been done in the reference design would already be great.


Best regards