Please refre to the information below:
In CMOS Dual Port Full Duplex Mode(the Figure 11) of AD9361 Interface Spec v2.5
1. Did position change of P0_D[11:0] and P1_DP[11:0] ?
But the Figure 11 above the location of P0_D[11:0] and P1_D[11:0] is different from the datasheet.
The location of the two digital interface are in direct opposition to each other(datasheet & App. Note)
2. In Dual Port Full Duplexer Mode(Full port) of CMOS Level,
Is P0_D[11:0] output for RX data of AD9361?
Is P1_D[11:0] input for TX data of AD9361?
Which position is right, P0_D and P1_D?