AnsweredAssumed Answered

DCPLB page size 4MB leads to target disconnect and VisualDSP-crash

Question asked by adt1 on Sep 23, 2010
Latest reply on Oct 3, 2010 by StuartS

Hi,

 

i have a problem with the cplb data page size. I have configured my cpld table for my L3-Memory (bank1):

...

{0x02800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},

{0x02c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},

...

 

In this memory i store data received from the PPI. However, if i run my programm, my target disconnects after some seconds and the whole VisualDSP crashes. It doesn't matter if the data cache is enabled or disabled.

 

 

When i use the following cbld tab configuration instead, everything works fine:

...

{0x02800000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
{0x02900000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
{0x02a00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
{0x02b00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},

...

 

CoreA and CoreB do interprocessor communications through L2 shared memory and IMDMA, but i cant see a link betweent this two issues.

Can anyone explain this behavior?

 

DSP: BF561

Visual DSP 5.0 Update 8

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