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Logic level translation with ADG3308 @ 100MHz

Question asked by upc-cd6 on Sep 4, 2014
Latest reply on Sep 4, 2014 by seanbrown

Good morning!


I need to interface a communication bus between an ASIC and a FPGA. The ASIC io's are 1.2V single ended and the FPGA is 3.3V single ended. I'm considering the use of ADG3308 for logic level translation (1.2V <-> 3.3V). My concern is about the maximum clock frequency that can be achieved. Is it possible to run signals up to 100MHz with ADG3304?