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AD9361- PLL update correction word reg 28E & 28F (Fractional > 0)

Question asked by FreddyS on Sep 2, 2014
Latest reply on Oct 23, 2014 by FreddyS

Dear supporter

Please refre to the attached DOC file describing the settings and expected output frequencies with plots and setup as described below:
            1. In positive correction the algorithm is working correctly.

    1. If the fractional is different than 0 the algorithm is working correctly.

 

    1. In fractional equal to 0 and negative correction:

 

      1. There is a shift in the correction value around 34Hz when we are using reg 28e & 28f.

 

      1. If we will insert main RF freq of 2599.999984MHz the value of reg 273 is EA.

 

      1. If we are using reg 28e & 28f with -16Hz correction the value of reg 273 is F9.

 

  reg 274 is FF and reg 275 is 7F. 

 

      1. In this case the value of  fractional reg (273-275) is 7FFFF9 (h) = 8,388,601 this value is bigger than the modulus 8388593.

 

It looks like there is a problem in the algorithm of the RF PLL update when using the correction word reg 28E and 28F.

 

What could be the reason?

Thanks for your support

Freddy

 

 

 

 

 

 

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