AnsweredAssumed Answered

Output timing of ADN2817 CDR chip

Question asked by MJHolmes on Sep 21, 2010
Latest reply on Sep 22, 2010 by enash

I'm designing a board with eight ADN2817 CDR chips. Trying to determine the expected output timing (clock to data) of the CML outputs. References to the data sheet.

 

Figure 2 on page 8 shows the clock and data, and labels a setup time and hold time.

 

The specs in table 3 on page 5 claim typical values of 200 ps for both for at room temp.

 

Well, OK, suppose I have a 1 Gbps signal. That's a data period of 1000 ps.

 

The clock rising edge can't be 200 ps after the data transition *and* 200 ps before the next data transition, so which is the dominant spec here?

 

Or could the clock rising edge be anywhere within a window defined by 200 ps after the data transition and 200 ps before the next data transition as shown in this image. In other words, does the datasheet only guarantee the clock will rise at least 200 ps after the data transition and at least 200 ps before the next data transition.

 

x.gif

 

I would hope not because that's a pretty loose spec. I need to make sure the chips downstream from this are happily timed. The 200ps after the data transition is good, but 200 ps before the next data transition could be a problem in my case.

 

So given a data rate (say 1 Gbps) that is less than the max capability of the chip (2.7 Gbps), what is the real window for clock rising edge versus data transitions on the CML outputs?

 

Thanks in advance!

Outcomes