Please could you advise me on the ad9361_calculate_ rf_clock_chain function in the No-OS driver code for the FMCOMMS2/3 FPGA reference design.
I understand the constraints for the BBPLL (needs to be 715 to 1.43GHz) and the Data Output (sample rate) max (2 RX & TX ports enabled, FDD, DDR) is 30.72MSPS.
I am trying to understand the methods of setting up the BBPLL and all other clocks including the sample rate clock. I can see two methods of configuring the sample rate:
1) Using the console to enter desired sample rate
2) Editing the init structure in main.c
In both cases, what is the profile used for programming the ADC clock, i.e. for the console entry, does the ad9361_calculate_ rf_clock_chain function try to program the ADC & DAC clocks to the highest frequency possible? At what point should the function decide it needs to use half band filters? Are there any profile guides available (power, performance, etc.) ?
I'm no software expert, but can the ad9361_calculate_ rf_clock_chain function be given a preference how to configure the chain? Does is consider the bandwidth requirement? E.g. is HB1 enabled prior to HB2?
Alsothe BBPLL divider can be up to 128, therefore in the reference design why wouldn't I choose to divide BBPLL_CLK by 32 to derive the 30.72MHz ADC_CLK if I wish to save power (if high bandwidth is not a requirement)? Is this possible?
Other questions that are related:
What is the performance of the ADC/DAC v clock frequency?
Is there an optimum performance and max/min frequency limits for the ADC and DAC?
What is the Baseband performance with & without the digital filter chain?