I can see that a lot of progress is done on the c5soc kit in connection with the fmcomms2 board. Is it possible to get a status on how much of the HDL design is actually working? Is the axi_ad9361, and dmac components functional?
I can see from this commit:
that SPI has been moved from the HPS to an FPGA implementation. Why is that? Clock frequency?
We have earlier heard from our supplier that the DMAC and SPI parts of the design was buggy. Are these fixed with the last weeks commits?
Thank you for the great progress on this.