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ADV7181D DDR_CLK_DEL[3:0] Register

Question asked by daisu on Sep 1, 2014
Latest reply on Sep 16, 2014 by daisu

Hello all,


1. Can DDR_CLK_DEL[3:0] set delay of output data for output clock (LLC) ?

2. If there is any register to set amount of delay , please let me know about relationship of register setting value and delay