1. Can DDR_CLK_DEL[3:0] set delay of output data for output clock (LLC) ?
2. If there is any register to set amount of delay , please let me know about relationship of register setting value and delay
The bits do nothing-- they are leftover from documentation carried from older parts and will be removed in the next revision so you observations make sense.
1) That control is only for DDR mode and adjusts the clock edge versus the data. It doesn't delay anything.. just shifts the data relative to the clock edge. Think of it as a phase adjustment.
2) DDR_CLK_DEL[3:0] does represent a fixed amount of delay but I don't see it documented anywhere what the bit values correspond to. I'll check.
1) Thank you for your advice.
2) Please tell me what the value of the bit supports.
Please let me know one more advice.
We set DDR mode 12bit output.
We can not find change of the relationship between clock and data when we set the value of DDR_CLK_DEL.
If there is any control signal to enable DDR_CLK_DEL[3:0], could you give me advice .
Thank you for your advice.
I understood that output data is not changed even if asked register is changed.
I have one questions about Register.
Could you tellm the register which we can set phase of output data to clock ?
I need the information for alignment of input timing to FPGA.
There is no output phase adjustment for the pixel port.
Thank you for an answer.
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