Without meaning to be pedantic it appears to me that the timing diagrams depicted in figure 66 are incorrect. for example the very first timing waveform on page 95 says 1R1T, DDR, Single Port with register 12 programmed to 0x2C. This would select a SDR as per register 0x012 bit definitions. Also the diagram only shows the data changing at the clock rate which also points to a SDR mode of operation.
If a customer wanted to use this mode to process 1R1T TX and RX signals at a 30.72MHz sample rate I assume the DDR option would need to be used. The DATA_CLK and FB_CLK would need to be 61.44MHz calculated as follows;
TXNRX = low, IQ Data RX Path in one DATA_CLK cycle,then TXNRX Toggled high then IQ data TX Path clocked by FB_CLK for one cycle.
I suspect the RX_FRAME and TX_FRAME signals are kind of academic at these rates?
My concern is if the above understanding is correct, which clock should be used to toggle TXNRX , DATA_CLK or the FB_CLK?