I have a question pertaining to the drive strength of the analog outputs of the ADXL335 3-axis analog accelerometer. The circuit is as follows: The analog outputs of the ADXL335 are connected to the inputs of a LMV324 Quad Op-amp in unity-gain configuration. The outputs of the op-amp are connected to the inputs of a ADS8332 Analog-Digital converter. The digital outputs from the ADC are then connected to an I/O pin on a Lattice XP2-8E FPGA. My question is: are the op-amp buffers required between the accelerometer and the ADC? They were placed as a precaution as we were unsure that the drive strength of the accelerometer was enough for the ADC inputs. We are now looking to shrink down the size of the board by removing the op-amps.
If you have any other questions or require more details, please let me know.