AnsweredAssumed Answered

ZC706 / AD9361 - FMCOMMS2

Question asked by leonardd on Aug 25, 2014
Latest reply on Aug 26, 2014 by AdrianC

I'm having problems rebuilding the design with the tcl scripts I keep getting the following errors:

 

I'm using Vivado 2014.2

 

I did have to change "processing_system7:5.3 sys_ps7 to processing_system7:5.4 sys_ps7 since it was giving me an error that the 5.3 was out of date.

 

L

 

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

source ./system_project.tcl

# source ../../scripts/adi_env.tcl

## set ad_hdl_dir  "../../.."

## set ad_phdl_dir "../../.."

## if [info exists ::env(ADI_HDL_DIR)] {

##   set ad_hdl_dir $::env(ADI_HDL_DIR)

## }

## if [info exists ::env(ADI_PHDL_DIR)] {

##   set ad_phdl_dir $::env(ADI_PHDL_DIR)

## }

# source $ad_hdl_dir/projects/scripts/adi_project.tcl

## set xl_board "none"

## proc adi_project_create {project_name} {

##

##   global ad_hdl_dir

##   global ad_phdl_dir

##   global xl_board

##

##   set xl_board "none"

##   set project_part "none"

##   set project_board "none"

##

##   if [regexp "_ml605$" $project_name] {

##     set xl_board "ml605"

##     set project_part "xc6vlx240tff1156-1"

##     set project_board "ml605"

##   }

##   if [regexp "_ac701$" $project_name] {

##     set xl_board "ac701"

##     set project_part "xc7a200tfbg676-2"

##     set project_board "xilinx.com:artix7:ac701:1.0"

##   }

##   if [regexp "_kc705$" $project_name] {

##     set xl_board "kc705"

##     set project_part "xc7k325tffg900-2"

##     set project_board "xilinx.com:kintex7:kc705:1.1"

##   }

##   if [regexp "_vc707$" $project_name] {

##     set xl_board "vc707"

##     set project_part "xc7vx485tffg1761-2"

##     set project_board "xilinx.com:virtex7:vc707:1.1"

##   }

##   if [regexp "_kcu105$" $project_name] {

##     set xl_board "kcu105"

##     set project_part "xcku040-ffva1156-2-e-es1"

##     set project_board "not-applicable"

##   }

##   if [regexp "_zed$" $project_name] {

##     set xl_board "zed"

##     set project_part "xc7z020clg484-1"

##     set project_board "em.avnet.com:zynq:zed:d"

##   }

##   if [regexp "_zc702$" $project_name] {

##     set xl_board "zc702"

##     set project_part "xc7z020clg484-1"

##     set project_board "xilinx.com:zynq:zc702:1.0"

##   }

##   if [regexp "_zc706$" $project_name] {

##     set xl_board "zc706"

##     set project_part "xc7z045ffg900-2"

##     set project_board "xilinx.com:zynq:zc706:1.1"

##   }

##

##    if [regexp "_mitx045$" $project_name] {

##     set xl_board "mitx045"

##     set project_part "xc7z045ffg900-2"

##     set project_board "not-applicable"

##   }

##

##   # planahead - 6 and down

##

##   if {$xl_board eq "ml605"} {

##

##     set project_system_dir "./$project_name.srcs/sources_1/edk/$xl_board"

##

##     create_project $project_name . -part $project_part  -force

##     set_property board $project_board [current_project]

##

##     import_files -norecurse $ad_hdl_dir/projects/common/ml605/system.xmp

##

##     generate_target {synthesis implementation} [get_files $project_system_dir/system.xmp]

##     make_wrapper -files [get_files $project_system_dir/system.xmp] -top

##     import_files -force -norecurse -fileset sources_1 $project_system_dir/system_stub.v

##

##     return

##   }

##

##   # vivado - 7 and up

##

##   set project_system_dir "./$project_name.srcs/sources_1/bd/system"

##

##   create_project $project_name . -part $project_part -force

##   if {$project_board ne "not-applicable"} {

##     set_property board $project_board [current_project]

##   }

##

##   set lib_dirs $ad_hdl_dir/library

##   if {$ad_hdl_dir ne $ad_phdl_dir} {

##     lappend lib_dirs $ad_phdl_dir/library

##   }

##

##   set_property ip_repo_paths $lib_dirs [current_fileset]

##   update_ip_catalog

##

##   create_bd_design "system"

##   source system_bd.tcl

##

##   save_bd_design

##   validate_bd_design

##

##   generate_target {synthesis implementation} [get_files  $project_system_dir/system.bd]

##   make_wrapper -files [get_files $project_system_dir/system.bd] -top

##   import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v

## }

## proc adi_project_files {project_name project_files} {

##

##   global ad_hdl_dir

##   global ad_phdl_dir

##

##   add_files -norecurse -fileset sources_1 $project_files

##   set_property top system_top [current_fileset]

## }

## proc adi_project_run {project_name} {

##

##   global ad_hdl_dir

##   global ad_phdl_dir

##   global xl_board

##

##   # planahead - 6 and down

##

##   if {$xl_board eq "ml605"} {

##

##     set project_system_dir "./$project_name.srcs/sources_1/edk/$xl_board"

##

##     set_property strategy MapTiming [get_runs impl_1]

##     set_property strategy TimingWithIOBPacking [get_runs synth_1]

##

##     launch_runs synth_1

##     wait_on_run synth_1

##     open_run synth_1

##     report_timing -file timing_synth.log

##

##     launch_runs impl_1 -to_step bitgen

##     wait_on_run impl_1

##     open_run impl_1

##     report_timing -file timing_impl.log

##

##     # -- Unable to find an equivalent

##     #if [expr [get_property SLACK [get_timing_paths]] < 0] {

##     #  puts "ERROR: Timing Constraints NOT met."

##     #  use_this_invalid_command_to_crash

##     #}

##

##     export_hardware [get_files $project_system_dir/system.xmp] [get_runs impl_1] -bitstream

##

##     return

##   }

##

##   # vivado - 7 and up

##

##   set project_system_dir "./$project_name.srcs/sources_1/bd/system"

##

##   set_property constrs_type XDC [current_fileset -constrset]

##

##   launch_runs synth_1

##   wait_on_run synth_1

##   open_run synth_1

##   report_timing_summary -file timing_synth.log

##

##   set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]

##   set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]

##   set_property STRATEGY "Performance_Explore" [get_runs impl_1]

##

##   launch_runs impl_1 -to_step write_bitstream

##   wait_on_run impl_1

##   open_run impl_1

##   report_timing_summary -file timing_impl.log

##

##   #get_property STATS.THS [get_runs impl_1]

##   #get_property STATS.TNS [get_runs impl_1]

##   #get_property STATS.TPWS [get_runs impl_1]

##

##   if [expr [get_property SLACK [get_timing_paths]] < 0] {

##     puts "ERROR: Timing Constraints NOT met."

##     use_this_invalid_command_to_crash

##   }

##

##   export_hardware [get_files $project_system_dir/system.bd] [get_runs impl_1] -bitstream

## }

# adi_project_create fmcomms2_zc706

INFO: [Project 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.

Current project path is 'c:/ProjectsSVN/DataLinkModem/xilinx/ad9361_git_hdl/hdl-master/projects/fmcomms2/zc706'

INFO: [Project 1-518] Migrating old board value xilinx.com:zynq:zc706:1.1 to new board_part xilinx.com:zc706:part0:1.0

INFO: [IP_Flow 19-234] Refreshing IP repositories

INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/ProjectsSVN/DataLinkModem/xilinx/ad9361_git_hdl/hdl-master/library'.

INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2014.2/data/ip'.

Wrote  : <c:/ProjectsSVN/DataLinkModem/xilinx/ad9361_git_hdl/hdl-master/projects/fmcomms2/zc706/fmcomms2_zc706.srcs/sources_1/bd/system/system.bd>

create_bd_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1336.602 ; gain = 0.000

## source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl

### set DDR [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR]

### set FIXED_IO [create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO]

### set IIC_MAIN [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_MAIN]

### set GPIO_I [create_bd_port -dir I -from 31 -to 0 GPIO_I]

### set GPIO_O [create_bd_port -dir O -from 31 -to 0 GPIO_O]

### set GPIO_T [create_bd_port -dir O -from 31 -to 0 GPIO_T]

### set hdmi_out_clk    [create_bd_port -dir O hdmi_out_clk]

### set hdmi_hsync      [create_bd_port -dir O hdmi_hsync]

### set hdmi_vsync      [create_bd_port -dir O hdmi_vsync]

### set hdmi_data_e     [create_bd_port -dir O hdmi_data_e]

### set hdmi_data       [create_bd_port -dir O -from 23 -to 0 hdmi_data]

### set spdif           [create_bd_port -dir O spdif]

### set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 sys_ps7]

### set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZC706}] $sys_ps7

INFO: [PS7-1] Applying Board Preset ZC706...

### set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7

### set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7

### set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7

INFO: [PS7-6] Configuring Board Preset part0. Please wait ......

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'PCW QSPI GRP IO1 ENABLE(PCW_QSPI_GRP_IO1_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'PCW QSPI GRP SINGLE SS ENABLE(PCW_QSPI_GRP_SINGLE_SS_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'PCW QSPI PERIPHERAL ENABLE(PCW_QSPI_PERIPHERAL_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

INFO: [IP_Flow 19-3438] Customization errors found on '/sys_ps7'. Restoring to previous valid configuration.

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'PCW QSPI GRP IO1 ENABLE(PCW_QSPI_GRP_IO1_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'PCW QSPI GRP SINGLE SS ENABLE(PCW_QSPI_GRP_SINGLE_SS_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'PCW QSPI PERIPHERAL ENABLE(PCW_QSPI_PERIPHERAL_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

INFO: [IP_Flow 19-3447] Customization errors found during restoring IP '/sys_ps7' to previous valid configuration.

ERROR: [IP_Flow 19-3439] Failed to restore IP '/sys_ps7' customization to its previous valid configuration.

ERROR: [BD 41-245] set_property error - Validation failed for parameter 'PCW QSPI GRP IO1 ENABLE(PCW_QSPI_GRP_IO1_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

Validation failed for parameter 'PCW QSPI GRP SINGLE SS ENABLE(PCW_QSPI_GRP_SINGLE_SS_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

Validation failed for parameter 'PCW QSPI PERIPHERAL ENABLE(PCW_QSPI_PERIPHERAL_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

Customization errors found on '/sys_ps7'. Restoring to previous valid configuration.

Validation failed for parameter 'PCW QSPI GRP IO1 ENABLE(PCW_QSPI_GRP_IO1_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

Validation failed for parameter 'PCW QSPI GRP SINGLE SS ENABLE(PCW_QSPI_GRP_SINGLE_SS_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

Validation failed for parameter 'PCW QSPI PERIPHERAL ENABLE(PCW_QSPI_PERIPHERAL_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

Customization errors found during restoring IP '/sys_ps7' to previous valid configuration.

Failed to restore IP '/sys_ps7' customization to its previous valid configuration.

 

INFO: [Common 17-17] undo 'set_property'

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'PCW QSPI GRP IO1 ENABLE(PCW_QSPI_GRP_IO1_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

qspi mutext : Conflict from - and -

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'PCW QSPI GRP SINGLE SS ENABLE(PCW_QSPI_GRP_SINGLE_SS_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

qspi mutext : Conflict from - and -

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'PCW QSPI PERIPHERAL ENABLE(PCW_QSPI_PERIPHERAL_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

qspi mutext : Conflict from - and -

INFO: [IP_Flow 19-3438] Customization errors found on '/sys_ps7'. Restoring to previous valid configuration.

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'PCW QSPI GRP IO1 ENABLE(PCW_QSPI_GRP_IO1_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'PCW QSPI GRP SINGLE SS ENABLE(PCW_QSPI_GRP_SINGLE_SS_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'PCW QSPI PERIPHERAL ENABLE(PCW_QSPI_PERIPHERAL_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

INFO: [IP_Flow 19-3447] Customization errors found during restoring IP '/sys_ps7' to previous valid configuration.

ERROR: [IP_Flow 19-3439] Failed to restore IP '/sys_ps7' customization to its previous valid configuration.

ERROR: [BD 41-245] set_property error - Validation failed for parameter 'PCW QSPI GRP IO1 ENABLE(PCW_QSPI_GRP_IO1_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

qspi mutext : Conflict from - and -

Validation failed for parameter 'PCW QSPI GRP SINGLE SS ENABLE(PCW_QSPI_GRP_SINGLE_SS_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

qspi mutext : Conflict from - and -

Validation failed for parameter 'PCW QSPI PERIPHERAL ENABLE(PCW_QSPI_PERIPHERAL_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

qspi mutext : Conflict from - and -

Customization errors found on '/sys_ps7'. Restoring to previous valid configuration.

Validation failed for parameter 'PCW QSPI GRP IO1 ENABLE(PCW_QSPI_GRP_IO1_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

Validation failed for parameter 'PCW QSPI GRP SINGLE SS ENABLE(PCW_QSPI_GRP_SINGLE_SS_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

Validation failed for parameter 'PCW QSPI PERIPHERAL ENABLE(PCW_QSPI_PERIPHERAL_ENABLE)' with value '1' for BD Cell '/sys_ps7'.

qspi mutext : Conflict from - and -

Customization errors found during restoring IP '/sys_ps7' to previous valid configuration.

Failed to restore IP '/sys_ps7' customization to its previous valid configuration.

 

 

    while executing

"rdi::add_properties -dict {CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0} /sys_ps7"

    invoked from within

"set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7"

    (file "../../../projects/common/zc706/zc706_system_bd.tcl" line 31)

 

    while executing

"source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl"

    (file "system_bd.tcl" line 2)

 

    while executing

"source system_bd.tcl"

    (procedure "adi_project_create" line 94)

    invoked from within

"adi_project_create fmcomms2_zc706"

    (file "./system_project.tcl" line 7)

Outcomes