This is a repost, with additional detail, at the request of PaulS.
We are experiencing HDMI compliance 1.4b Test 8-7 (jitter injection) failures at 27MHz/480p and at 222.75MHz/1080p60 deep color (and we are not presently certifying for 297MHz.)
The TMDS clock locking becomes unstable at both of these frequencies; when the pixel clock does occasionally lock, DE lock is unstable as well. We are making all of the recommended settings in both cases.
Our DUT passes all electrical tests and all of the other format tests. These are the only failures.
We are not using the ADI software driver; the product is a custom embedded system. We have not attempted to reproduce the problem with an evaluation board, as this would require travel to the certification site plus lab time expenses of $500/hour for the test.
If there is any ADI software driver code available other than that which simply loads scripts for the evaluation board, we have never seen it.
Most of the register settings which are related to TMDS PLL lock stability are undocumented (i.e. they just receive 'recommended' magic values). Since we have no idea how they really work, we have very little to go on in solving this problem.
We are looking for any information which may help to solve the issue quickly as the test lab has a relatively short time limit for resubmission.
One specific question: We only just obtained Rev 1.5 of the "recommended settings" document, which contains a procedure for setting NEW_VS_PARAM. Previously, it was recommended to always set this bit, which we were doing. Will implementing the section 1.3.7 logic which only sets it when total H-blank > line-length/2 potentially solve this issue?