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can't get hdl/projects/fmcomms2/zc702 compile to work properly

Question asked by stimm on Aug 22, 2014
Latest reply on Oct 23, 2014 by rejeesh

I'm working on a AD9361 project using the ZC702 and fmcomms2 eval cards.I’m trying to compile the fmcomms2 HDL reference design and run it on our systems to make sure I can compile it okay. My plan is then to start making changes to add the logic we want in the design. When I compile the Github.com/analogdevicesinc/fpgahdl_xilinx/cf_ad9361_zc702 design using ISE/XPS I’m able to successfully generate a bit file, export it to SDK, and generate a BOOT.bin. I load it onto the SD card and everything runs just fine.

 

According to the wiki page the Github.com/analogdevicesinc/hdl is the repo to use for vivado so I cloned that and tried compiling the various library modules, at least the ones that had a <module>_ip.tcl file. All of them compiled fine except for axi_fifo2s which gets an error. I get the error shown below when using either vivado 2013.4 or 2014.1

 

NFO: [IP_Flow 19-2228] Inferred bus interface "axi" of definition type "xilinx.com:interface:aximm:1.0".

INFO: [IP_Flow 19-2228] Inferred bus interface "m" of definition type "xilinx.com:interface:aximm:1.0".

INFO: [IP_Flow 19-2228] Inferred bus interface "axi_signal_reset" of definition type "xilinx.com:signal:reset:1.0".

INFO: [IP_Flow 19-2228] Inferred bus interface "axi_signal_clock" of definition type "xilinx.com:signal:clock:1.0".

INFO: [IP_Flow 19-2228] Inferred bus interface "m_signal_clock" of definition type "xilinx.com:signal:clock:1.0".

ipx::package_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 876.672 ; gain = 0.000

INFO: [#UNDEF] INFO: [#UNDEF] # ipx::infer_bus_interfaces {{xilinx.com:interface:aximm:1.0}} [ipx::current_core]

INFO: [IP_Flow 19-2228] Inferred bus interface "axi" of definition type "xilinx.com:interface:aximm:1.0".

INFO: [IP_Flow 19-2228] Inferred bus interface "m" of definition type "xilinx.com:interface:aximm:1.0".

WARNING: [IP_Flow 19-3164] Cannot infer address space 'axi'. The address space object already exists

.

WARNING: [IP_Flow 19-3166] Cannot infer memory map 'm'. The memory map object already exists

.

INFO: [IP_Flow 19-2228] Inferred bus interface "axi_signal_reset" of definition type "xilinx.com:signal:reset:1.0".

INFO: [IP_Flow 19-2228] Inferred bus interface "axi_signal_clock" of definition type "xilinx.com:signal:clock:1.0".

INFO: [IP_Flow 19-2228] Inferred bus interface "m_signal_clock" of definition type "xilinx.com:signal:clock:1.0".

ERROR: [Common 17-39] 'ipx::infer_bus_interfaces' failed due to earlier errors.

 

while executing

"ipx::infer_bus_interfaces {{xilinx.com:interface:aximm:1.0}} [ipx::current_core]"

(file "axi_fifo2s_ip.tcl" line 16)

 

 

If I ignore this error and compile the projects/fmcomms2/zc702 design it runs without errors. I generate a bit file, export it to SDK, generate a BOOT.bin file, and place it on the SD card but when I boot the card I don’t see any of the fmcomms information in the ADI IIO Oscilloscope gui. I assume the application can’t talk to the fpga logic so doesn’t display the relevant info on the oscilloscope.

 

  Is Github.com/analogdevicesinc/hdl/projects/fmcomms2/zc702 the equivalent to Github.com/analogdevicesinc/fpgahdl_xilinx/cf_ad9361_zc702, one is for vivado and one for ISE or are the designs different? The wiki page leads me to believe they are the same but I’m not sure. Could the compile error of the library module be the problem?

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