I replied to a similar discussion but did not get answer on it (ADV7619 - HDMI Compliance Test Failed), so I am starting a new thread.
We use the ADV7619 in one of our products and are failing HDMI CTS test 8-7 TMDS jitter tolerance for pixel clocks of 27MHz and 297MHz. We pass for all other intermediate pixel clock frequencies: 74.25MHz, 148.5MHz and 222.75MHz.
According to our system logs during the failure, the ADV7619 PLL lock status is not stable, and keeps toggling between lock/not locked status.
We are following the recommended settings v1.4. I checked recommended settings v1.5 and the only real change is about 68 6F 0C changed to 68 6F 08, which I do not think has an impact on the jitter issue.
What do you advise? Should we try other equalization settings than the recommendations in the document? Are there other parameters that could have an effect on jitter tolerance?
Thank you in advance.