The circuit diagram is:
- The supply voltage:
+12V&-9V, OPA2227 used as a buffer.
- Input voltage is low
frequency pulse (50us period), ever tried with step input.
- When input with 0-1.3V,
no problem, the measured voltage of TP is almost same as input, ie, 0-1.3V.
- When input 1.3V or
higher, output: 1.3V+offset, offset is >1V.
- Same for 2 tested channels (they just test 2 channels, while rest unconnected channels have PU).
- Old design is ADG508F, no problem
- they tried to optimize the circuit for better performance of ADG1208.
I have doubt on the power up sequence to the ADG part in the circuit to possible cause latch-up(ADG1208 is not latch-up proof), but will the latch-up make the ADG1208 act to get result escribed above?