I am currently testing the AD9361 for a Wifi application. I read through a couple of posts on using the transceiver for TDD applications and had some questions:
1. In FDD independent mode, is it advisable to have the Tx / Rx synthesizers configured to the same frequency. Since the synthesizers are always on will this result in any performance degradation / calibration issues?
2. Since the Tx path takes at least 18us to turn on, is it possible to leave the Tx path always on to reduce the Rx to Tx switching time?
3. In case the FDD fast lock profiles are being used, I read on one of the discussions that in FDD mode with 40MHz reference clock frequency the lock time is about 20us. Is the lock time less for frequencies <100MHz apart? How much would the lock time reduce to if using 80MHz reference clock frequency?
4. The ENSM_v2.2 document mentions that the BBIC must allow enough time for Tx / Rx flush. How do I compute the data flush / zero data forcing times before and after data transmission? Does this time add to the 18us required for DAC powered up?