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AD9739A + ML605 Fifo Buffer

Question asked by rosanahm on Aug 21, 2014
Latest reply on Sep 9, 2014 by rejeesh

I am working with the reference design using the AD9739a DAC and ML605 on the wiki page (http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9739a). I am trying to output a signal I have stored in DDR. I have noticed some strange behaviour. I will try to describe the issue below:

 

I load DDR with 131072 16-bit sample points of a waveform (total of 262144 bytes). I configure dma to transfer this data and continuously loop around the 131072 sample points:

 

"dmaSetup.EnableCircularBuf = 1;

dmaSetup.HoriSizeInput = 64;

dmaSetup.VertSizeInput = 4096;

dmaSetup.Stride = 64;

dmaSetup.FrameDelay = 0;

dmaSetup.EnableSync = 0;

dmaSetup.EnableFrameCounter = 0;

dmaSetup.FixedFrameStoreAddr = 0;

dmaSetup.PointNum = 0;

"

 

If I load DDR with a sinusoid which has 128 sample points in one period, the output looks fine when measured using an oscilloscope (see ad9739a_ml605_128points attached).

 

If I load DDR with a sinuoid which has 129 sample points in one period, the output has "glitches" (refer to ad9739a_ml605_disjointed). I have verified that this "glitch" isn't from having a non-integer number of periods in the 131072 point long waveform because this glitch occurs far more frequently.

 

So now I load DDR with a waveform that has a 128-point long sinusoid, followed by a 64-point long sinusoid, followed by a 32-point lonf sinusoid, followed by a 16-point long sinusoid followed by a 8-point long sinusoid, all of this repeated until the memory block is full. I found the "glitchs" (refer to ad9739a_ml605_glitches and glitches_zoom) to occur at about every 1507 samples in memory (~6030 oscilloscope samples / 4 to take into account different in sampling rate).

 

What can be causing this? Can this be related to the memory buffer size? The code in cf_ddsv_vdma shows that the buffer is 1536 samples long :

 

 

  cf_mem #(.DW(96), .AW(8)) i_mem (

 

    .clka (vdma_clk),

    .wea (vdma_wr),

    .addra (vdma_waddr),

    .dina (vdma_wdata),

    .clkb (dac_div3_clk),

    .addrb (dds_raddr),

    .doutb (dds_rdata_s));

How can I fix this behaviour? I am truly grateful for any guidance you can provide.

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