I using CM03F'S ADC to sampling a sine wave signal ,and I want to operate in DMA mode to transfer 512 bytes to the internal sram.
So I use GPTMR0 to be ADC0 trigger,and config the DMA mode enable.Then I set the ADCC_CTL.EN bit to enable the ADC.But the problem is the ADC0 only converted one time,then the ADCC_FISTAT.FINT0 change to '1'.
The Hardware Reference Manual said "Note that the frame completion status bits must be acknowledged by clearing it before the next trigger appears. Otherwise, the trigger is ignored, and the trigger overrun error condition is flagged.".So I want to clear
the ADCC_FISTAT.FINT0 bit.But when I write 1 to the ADCC_FIMSK_CLR.FINT0 bit to clear the ADCC_FIMSK.FINT0 bit.The ADCC_FIMSK.FINT0 bit always '1',The ADC only transfer one Frame,because it ignored other triggers.I think may be I make some mistakes.I see the EE-365: Code example ,they use the DMA17/18 to clear the interrupt bit.I do it like the code example,but also can not cleared.
Would anyone give me some advise.