I have a general question regarding the ADF4351 chip. I am programming several frequencies across the range of 400 MHz to 4.3 GHz but I am having problems at frequencies above 2.2 GHz (when the VCO divider is 1). I do get some output power but the spectrum is very ugly and it appears to be an unlocked VCO at the low end of the tuning range. (i.e. ~550 MHz or ~1100 MHz… 2200 divided by 4 or 2) The digital lock detect (MUX output) indicates that the chip thinks it is locked. I started with a BSC clock set to 500 kHz but have since reduced this to 125 kHz with no changes in the output performance. Given that the PLL locks (and the output spectrum is good) when the divider is set to 2, 4, or 8 I think that my math is correct but I am unable to lock at the higher frequencies. Any advice is appreciated.