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ADSP-CM403F SPI FIFO

Question asked by kalaiselvan.s@hcl.com on Aug 19, 2014
Latest reply on Aug 20, 2014 by Prashant

Hi,

I am currently working on CM403F processor SPI module. In hardware reference manual page no(1400-1401) for Transmit FIFO Data Register and Receive FIFO Data Registers section i have little confusion on size of TFIFO and RFIFO. In manual the statement is

"The top level of the buffer is visible to programs as the 32-bit SPI_RFIFO register, but the size (number of word locations) of the receive FIFO is actually flexible with transfer word size. The size of the receive FIFO is 8 if word size is 8-bit, or the size is 4 if word size is 16-bit, or the size is 2 if word size is 32-bit."

 

Actually my understanding for the above is:

 

If the transfer word size 8-bit, FIFO size is 8 bit

If the transfer word size 16-bit, FIFO size is 16 bit

If the transfer word size 32-bit, FIFO size is 32 bit

 

If my understanding is correct then below statement is contradicting me:

 

1. "the size is 4 if word size is 16-bit, or the size is 2 if word size is 32-bit"

2. Hrm says, size = number of word locations but my understanding is its no of bits. isn't it?

 

Can anyone clarify on this?...

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