Does anybody have experience with a ADSP21469 design and 512 MByte DDR2 attached to it?
We want to connect 2 x Micron MT47H128M16 (2 Gb x 16) to the DDR2 interface. We are a bit concerned about signal integrity.
Does following statement in the hardware reference manual (p. 4-99) apply?
"Buffering Controller for Multiple DDR2s
If using multiples DDR2s or modules, the capacitive load will exceed the
controller’s output drive strength. In order to bypass this problem an
external register (SSTL18 class) can be used for decoupling by setting bit
24 in DDR2CTL0 register. This adds a cycle of data buffering to read and
We´d appreciate any feedback on this.