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FMCOMMS2 Reference design Clock Question

Question asked by wmaguire on Aug 19, 2014
Latest reply on Aug 19, 2014 by wmaguire

Hi all,


Just a question to verify my understanding of the DATA_CLK rate on the FMCOMMS2 reference design.  From viewing the code I see both receivers and transmitters are active, in otherwords the demo design is operating in 2RX2TX mode.   I also note that the sample rates for both TX and RX paths are set to 30.72MHz and operate in LVDS mode.   Therefore I deduce that the DATA_CLK will be 122.88MHz = 30.72MHz *2(for IQ) * 2 (two RX channels).  Is this corrrect?


I assume if the RF sampling remains at 30.72MHz and only one receiver is active then the DATA_CLK will be 61.44MHz,


Finally I assume the clock will be continuous and have a 50% duty cycle?