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Question on the AD9122 core

Question asked by tom_bdl on Aug 18, 2014
Latest reply on Aug 19, 2014 by tom_bdl
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As far as I can see, in the ADI reference design, the AD9122 gets 64 bits of input data from the DMA at every clock cycle of 491.52 MHz. I am trying to modify the AD9122 core so that it accepts 16 bits of data at every clock cycle, instead of 64 bits. In other words, I am trying to map the i0/q0 channel (which is 16 bits) to the input of the DAC. (I want to give the DAC one sample per 491.52 MHz clock, as opposed to 4 samples).


Can you please suggest a solution or let me know if this is possible to implement?