Hi, I know that the AD9361 has a channel bandwidth ranging from <200kHz to 56 MHz.
1) What is the minimum channel bandwidth it can be programmed for - below 200 kHz?
2) What are the issues to consider if we plan on using this chip for applications with channel bandwidth <100kHz.
3) What drives the min. bandwidth limit?
4) I assumed this min bandwidth was driven by the BB PLL frequency, is that right? If so, what is its minimum frequency achievable?