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About SYSREF & DIVCLK Signal in AD9625-2.5G ADC

Question asked by Sonu57 on Aug 18, 2014
Latest reply on Aug 19, 2014 by Sonu57

Hi,

 

I am planning to use AD9625-2.5G ADC part in my design. The output of this ADC shall be interfaced with the GTX bank of Virtex-7 FPGA by JESD204B interface.

 

I am having doubt in the interfacing of the clock signal to the FPGA.

 

1. Which clock shall be interfaced to the GTX bank of FPGA for JESD204b interface operation ?

 

2. The SYSREF signal period shall be integer multiple of LMFC or Frame Clock. The Frame clock & LMFC is generated from the sampling clock. If I will change the sampling clock, the SYSREF clock has to be changed as it's period shall be integer multiple of Sampling clock. So how to generate SYSREF clock from the sampling clock so that it's period will be integer multiple of  the period of Sampling clock ?

 

3. Where shall the SySREF signal be interfaced, with GTX bank of the Virtex-7 FPGA or normal IO bank of the Virtex-7 FPGA ?

 

4. There is a divide by clock DIVCLK is present which is a output clock. Is this the Frame clock for the JESD204B operation. If yes then where shall it be interfaced with GTX bank of the Virtex-7 FPGA or normal IO bank of the Virtex-7 FPGA ?

 

Regards

Soumya

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