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There are some errors to use the HDL code of the AD9361, please help.

Question asked by ADI_Wei on Aug 15, 2014
Latest reply on Aug 18, 2014 by AdrianC

Hardware: Zedboard, AD-FMCOMMS2-EBZ

Software: Vivado 2014.2, HDL code

Reference: http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/baremetal

http://wiki.analog.com/resources/fpga/docs/hdl/vivado

 

 

Step 1: Building the libraries and projects

 

Tcl Console command:

cd c:/github/library/axi_ad9361

source ./axi_ad9361_ip.tcl

cd c:/github/projects/fmcomms2/zed

source ./system_project.tcl

 

There are some errors show in below picture.

Vivado8.JPG

 

The project part is not coincided with the Zedboard part. Whether to revise it?

vivado_3.JPG

 

And there are some errors. For example,

[BD 5-216] VLNV is not supported for this version of the tools.The latest version is:5.4

How to modify this version to be compatible?

Vivado.JPG

 

 

Step 2: Open the Xilinx SDK for Vivado.Then the source code has been added. But there are some errors about the file parameters.h

Vivado8.JPG

 

Could you please help me to get rid of those errors? And please tell me the exactly steps to run the reference code by using of this hardware and software. Thanks.

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