Is the INT_L signal that is driven out from the ADV7401 synchronous with the output clock, LLC1? How do you select which registers result in the interrupt signal being toggled?
It is not defined if INT is synchronous with the output clock. It generally doesn't matter since the processor can normally handles edges or level interrupts.
From Table 112,
0x40 sets up the basic interrupt pin.
0x42, status registers latches on to what has caused the interrupt and can only be cleared by writes to their respective bits in 0x43 register
0x44 masks the respective interrupt sources from getting to the interrupt pin
On startup a CPU will
1) clear all interrupt sources via 0x43
2) configure the interrupt pin
3) set the mask register for those interrupts of interest, 0x44
The on an interrupt the CPU will
1) read status register 0x42,
2) process the interrupt and clear the bit via 0x43
When an interrupt occurs the CPU should check, process and clear all possible interrupt source before re-enabling it's interrupt input.
Not sure if this answered you question
Retrieving data ...