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AD7466- cs input

Question asked by kbm10 on Aug 14, 2014
Latest reply on Aug 14, 2014 by KarenNE

Hi All,


I am planning to use AD7466 in my application and I have a question about the cs input.


In order to take data out of the ADC after conversion, the CS signal can be low the whole time to obtain different sets of data or do I need to alternate between HIGH and LOW.


From the datasheet, what I can understand is, it needs to be alternated(HIGH and LOW like a square wave) at least after 16 SCLK clock cycles to take data out. This is because conversion begins at falling edge of the CS ? Is it correct ?


Thanks in advance.