Can you offer some help on these questions regarding the ADF4360-7 PLL? Here’s a quick rundown of what my customer is doing:
1) The design was taken from the eval board
2) There are 2 PLL’s on the board, one generates 775 MHz, the other 400 MHz (800 MHz internal with output divide by 2)
3) 10 MHz reference oscillator
4) The PFD is running at 200 kHz
1) Close in, they don’t see a reference spur at 200kHz, but there is a prominent one at 300 kHz.
2) Out of band, there are many spurs being generated at multiples of the Reference Frequency (30, 40, 50 … 170, 180, 190, 200 MHz)
The PLL’s lock, and the 300kHz ref spur, while odd, is not that big of a deal for them. It’s the out of band spurs, as they are falling within our IF passband and interfering with our signal. Please explain what is going on if you can.