We are using the quad video decoder ADV7181C for four camera inputs decoding and switching.
Input 1 = Non-standard resolution RS170 Camera
Input 2, 3, 4 = Standard NTSC / PAL Cameras
Decoder Output Format
DDR 8 bit-wide 4:2:2 YCbCr mode (this is how it is physically connected on our circuit board)
I believe we need to use the Component Processor (CP) inside ADV7181C for the non-standard resolution camera while the NTSC / PAL camera inputs can be automatically detected by the SDP core inside ADV7181C. According to the datasheet, the pixel data output format for the decoder is as follows:
SDP PIXEL DATA OUTPUT MODES
The SDP pixel data output modes are the following:
• 8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time codes and/or HS, VS, and FIELD
• 16-/20-bit YCrCb with embedded time codes and/or HS, VS, and FIELD
CP PIXEL DATA OUTPUT MODES
CP pixel data output modes include single data rate (SDR) and double data rate (DDR) as follows:
• SDR 8-/10-bit 4:2:2 YCrCb for 525i, 625i
• SDR 16-/20-bit 4:2:2 YCrCb for all standards
• DDR 8-/10-bit 4:2:2 YCrCb for all standards
As mentioned earlier, we are interfacing the decoder as DDR 8 bit-wide 4:2:2 YCbCr mode. I know this mode will work with the CP core when we have Camera 1 input (with non-standard resolution). My question is what happens when switch to an NTSC/PAL camera? Won't the decoder use the SDP core and then will the output format still be DDR or will it change to SDR? I want to make I have proper logic implemented in the FPGA to the capture incoming data.
Thanks for your help!