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Does the FMCOMMS2/3 reference design require IQ correction in the FPGA?

Question asked by andrew.dickson on Aug 12, 2014
Latest reply on Aug 19, 2014 by ACozma



I have recently managed to get the latest FMCOMMS2/3 AD No-OS reference design up and running on my Zedboard using Vivado2014.2. Previously I was using the FMCOMMS1 platform.


Illustrated in the Wiki HDL block diagram (see link: AD-FMCOMMS2-EBZ / AD-FMCOMMS3-EBZ / AD-FMCOMMS4-EBZ HDL Reference Design [Analog Devices Wiki]) the diagram shows the dc filter and IQ correction blocks in the RX paths that was required in the FMCOMMS1 platform.


Also in the Verilog HDL, there are still HDL files for this function in the latest version on GitHub.


From my understanding, I thought all this would be taken care of by the AD9361 chip in both RX and TX paths. Is this correct? If yes, how is this done by the chip (or reference where this is explained)? Is there any programming of the AD9361 required to perform this?


Please advise as I would rather remove this logic if it is no longer necessary and is just left in there from the FMCOMMS1 reference design.


Kind Regards,