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AD9910 Phase offset validation

Question asked by mantow on Aug 12, 2014
Latest reply on Aug 18, 2014 by Kevin.G

Hi Engineerzone,


I wish to seek some advice about how to validate the phase offset setting for a DRG-generated chirp, as well as in single-tone CW mode.


I'm using the AD9910 evaluation board which is clocked externally using 10 MHz and I enable the internal PLL for 1 GHz system clock operation. For any single tone in the Profiles we can specify the phase offset but I'd like to verify that the offset value which I'm invoking is as expected. I'm monitoring the DDS output directly on a scope. What is the best way of doing this ?



Many thanks in advance