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Customize reference design of ad-fcomms1-ebz

Question asked by McG on Aug 8, 2014
Latest reply on Sep 15, 2014 by rejeesh

Hi everyone,

I have a zedboard with a ad-fcomms1-ebz card. I successfully used the reference design found at analogdevicesinc/hdl · GitHub

Now my aim is to customize the design. Unfortunately i don't know verilog language but only VHDL, so I have some difficult to apply changes starting from the given design.

From a first view I have seen that:

    • In TX section I have 3 outputs (dac_clk_out, dac_frame_out, dac_data_out) and 1 input (dac_clk_in) for an amount of 34 pins.
    • For the RX section I have only inputs (adc_clk_in, adc_or_in, adc_data_in) coming from ADC, for an amount of 36 pins.
    • For reference clock there is a differential pair (clk_ref) generating 30 MHz (2 pins)
    • For communication I have I2C interface with two single ended signals (SCL and SDA). (2 pins)

  1. I think these are the only signals (74 pins towards FMC connector) I need to work with the board, right?
  2. I tried to create a new system composed only by a zynq processor, I2C interface, 30 MHz clock reference, dac_frame_out (with frameP=0 and frameN=1) and a 125 MHz dac_clk_out. But when I execute the no-OS drivers found at fpgahdl_xilinx/cf_xcomm_zed at master · analogdevicesinc/fpgahdl_xilinx · GitHub I have no problems with function XCOMM_InitI2C(&defInit) but I get an error in the functions XCOMM_Init(&defInit). I need particular configurations for I2C or is there something to do before to launch the script?
  3. In a previous discussion ( Format of data at DAC I & Q inputs ) there has been talk about AD9122 DAC. I didn't understand exactly the way to send the data to the DAC. In cited discussion the user said that we need of 4 samples (one for each sine wave) at 125 MHz in order to have a datarate of 500 MHz, so I think I need to use 16 DDR serdes channels to serialize 4 waves samples. In this way I send 64 bits at 125 MHz to the serdes, and the serdes send 16 bit to the dac at 500 MHz, right? But if my reasoning is right, I don't understand the figure shown at AD-FMCOMMS1-EBZ Functional Overview [Analog Devices Wiki] In fact the in the block "AD9122 PCORE" the four DDS' (two couples of I/Q signals) are added creating two signals. This means that I have only 2 waves not 4.... Where i get lost?


Thank you in  advance,


Best regard