I have looked in the data sheet and it is unclear what the sample rate for the ADCs are and how they are set
You have opened another thread that contains the same question (https://ez.analog.com/message/163259#163259). Let's continue the discussion there.
The information is not contained in the datasheet.
The ADC clock rate is set based on a number of criteria and constraints.
The sampling rate is based on the BBPLL output frequency range, desired output data rate, ADC sampling rate range and RF bandwidth.
The chip contains clock dividers and adjustable rate half band filters and FIR filters that allow to meet the above mentioned criteria and constraints.
Analog Devices provides device drivers that determine the required configuration and set the correct ADC sampling rate for different applications.
More information can be found in the device documentation (users manuals) available for download from analog.com. Download requires registration.
I realize it is not in the data sheet that is the reason for my post.
We have the manuals UG-570 and UG-671, but it is still not clear to me what the limits for the clock dividers and filters are.
What is the fastest sample rate I can get out of the ADC? How do I get there?
ADC sample rate range is: 10.5MHz (min) - 640MHz (max)
Output max data rate (output of Rx chain, not ADC output) is 61.44MHz
RHB3 decimation rates: 3,2,bypass
RHB2 decimation rates: 2, bypass
RHB1 decimation rates: 2, bypass
RFIR decimation rates: 4, 2, 1 or bypass
BBPLL range is 715MHz - 1430MHz
BBPLL divider ratio: min 2, max 64
Maximum ADC output data rate is not as important as receiver maximum output data rate of 61.44MHz. You have to configure digital filter decimation ratios in such a way as not to exceed 61.44MHz at the output. ADC output data rate varies based on how you configure digital filter decimation rates.
@tlili In the data sheet for the AD9361 under the parameter "Digital Data Timing (CMOS) the spec. is 61.44MHZ but in the section "Digtal Data Timint (LVDS)" the spec. is 245.76 MHz.
So is the speed really limited to only 61.44MHZ? for an output sample rate? or is it upto 245.76MHz using LVDS?
For CMOS the speed is 61.44MHz max. For LVDS the max speed is 245.76MHz.
You can find more detail in UG-570 starting on page 90. LVDS maximum clock rates are covered starting on page 108.
I have not tried this and it is purely from the datasheets but I think it is doable to do 61.44 MSPS.
The ADI part internally has a high sampling rate delta-sigma ADC. After halfband filters and all, you can get to a usable sample rate.
Working backwards from the interface to ADC gives us the following:
The LVDS bus runs at 245.76 MHz (max) at DDR but half-sample size per edge (6bits DDR is equivalent to 12 bit SDR). So the output is 245.76 MSPS. This is for 2 antenna ports. So each antenna has 122.88 MSPS.
Each antenna has I & Q samples. Therefore each I or Q comes up at 61.44 MSPS.
So how do we get to 61.44 MSPS?
I assume you are using dual antenna and full bandwidth in your application.
Program the following components as follows.
1. BBPLL @ 737.280 MHz
2. BBPLL divide by 2 to ADC (ADC @ 386.64 MHz)
3. RXHB3 decimate by 3 (122.88 MSPS)
4. RXHB2 no decimate
5. RXHB1 no decimate
6. RXFIR decimate by 2. (Output @ 61.44 MSPS)
Please note that this is for dual antenna operation.
There is another limitation for FIR filters such that the interpolation on the FIR filter affects the number of taps that can be used.
For a decimation of 1, only 64 taps are available. For decimation of 2 128 taps, and for 4 you can use the whole filter (256 taps.)
I am Bhaskar . I will be using ad9361 as a part of my sdr project . I am using zynq zc702 , hence I am going through the reference design and I have a few questions.
1.) As I understood till now , the filter configuration are set in the software are passed to the ad9361 board via SPI . The I and Q samples for a sine wave are generated within the software and passed to HDL core for ad9361 via dmac transfer for bit rearrangement(as the DAC on ad9361 is of 12 bit resolution). My question is where are we controlling the sample rate ? . In the AD9361_InitParam default_init_param we give the reference_clk_rate as 40 mega but we don't seem to use it anywhere. Please help me to understand about controlling sample rate as this will be the prime parameter in my case .
2.) There is a function ad9361_set_trx_path_clks in ad9361_api.h but we dont seem to use that either in the sample design , so how do we actually setting the rate of data transmission in the sample design?
3.) In my case I have developed a QPSK modem peripheral whose samples I want to up convert to a specific center frequency . In this how to communicate mu samples to DMAC rather then sending the pre generated sample as in reference design.
Moved to Linux software drivers.
Moved to no-OS drivers.
in UG 570 Table 10 pints out some common clock rates but does not give any limits. For example for LTE 20 it has a sample rate of 30.72 and the BBPLL is 983. but it does not cover what is the sample of the actual data or if we can bypass the HB2, HB1 or RX FIR filters.
If the BBPLL is runing at 983 is the ADC depicted on Figure 17 page 33. or UG570 running at 983 Msmps?
I would like to mark this question as answered since Hank was posting for me.
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