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AD9361 PLL N fractional 0

Question asked by FreddyS on Aug 7, 2014
Latest reply on Aug 21, 2014 by tlili

Dear Supporter

My customer is using the AD9361 . The problem reported is as follows:


We are using GPS to adjust the RF freq error.

We have a problem with FREQUENCY CORRECTION WORDS registers 24e, 24f, 28e and 28f.

We are using 40MHz REF clock and for the RF pll we multiply it by 2 (80MHz).

According to the Equation 1-4 in AD9361 RF and BBPLL user guide 2.4.

The desired freq is 2600MHz.

RF PLL = 2600*2^2 = 10400MHz.

PLL N integer = 10400/80 = 130 dec.

PLL N Fractional = 0 dec.

the GPS RF freq correction need to reduce the freq in 16Hz.



VCO Divider= 2^2 = 4

Delta LO  = -16 Hz

PLL Ref Freq = 80MHz

Correction = ROUND[(VCO Divider* Delta LO)/ PLL Ref Freq]*8388593,0]= -7 dec

2’s Complement = 1111 1111 1001 = FF9 h. 

Reg 24e & 28E = 1F h

Reg 24f & 28f = F9 h   

When we are inserting those values the signal is unstable and looks like the PLL isn’t lock.

( the lock indicator return lock)


When the PLL N Fractional isn’t 0 (for example 2590MHz) and we are inserting the same value to those registers the RF freq changes correctly the signal look OK. It seems like there is a problem when the PLL fractional is 0.

The same scenario is reproduced on AD9361 EVB.