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verilog file missing in HDL_Master

Question asked by ranjan.jk@nikhilon.com on Aug 6, 2014
Latest reply on Aug 7, 2014 by CsomI

Hello All,

 

While we started to compile HDL reference code provided in https://github.com/analogdevicesinc/hdl the following files are missing viz.

          altlvds_tx and altlvds_rx

 

but i tried constructing code for these missing files and here is my try as shown in below, please try to correct this or can it be uploaded in git for the above said missing files.

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module lvds_rx_wrapper (

  rx_in,

  rx_inclock,

  rx_deskew,

  rx_out,

  rx_outclock);

 

  input [1:0]  rx_in;

  input  rx_inclock;

  input  rx_deskew;

  output [7:0]  rx_out;

  output  rx_outclock;

 

  wire [7:0] sub_wire0;

  wire  sub_wire1;

  wire [7:0] rx_out = sub_wire0[7:0];

  wire  rx_outclock = sub_wire1;

 

  altlvds_rx altlvds_rx_component (

  .rx_deskew (rx_deskew),

  .rx_inclock (rx_inclock),

  .rx_in (rx_in),

  .rx_out (sub_wire0),

  .rx_outclock (sub_wire1));

  defparam

  altlvds_rx_component.intended_device_family = "APEX™20KE",

  altlvds_rx_component.number_of_channels = 2,

  altlvds_rx_component.deserialization_factor = 4,

  altlvds_rx_component.inclock_period = 1,

  altlvds_rx_component.registered_output = "ON";

 

endmodule

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Regards

J K Ranjan

Hardware Engineer

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