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Configuring the BBPLL on AD9361 to get data rate of 576 KHz

Question asked by sunilkumar on Aug 5, 2014
Latest reply on Sep 8, 2014 by s.kumar

Hello

For our application we want to configure the Data rate to 576 KHz, we are configuring AD9361 through the non- OS version of software (downloaded from github.com),

As per our calculation we are setting the BBPLL frequency 884.736 MHz with the divider value 32.

  1. BBPLL (set to 884.736MHz)   à (div 32)  to get  = 27.648MHz for ADC

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/* LO Control */

70000000UL, //rx_synthesizer_frequency_hz *** adi,rx-synthesizer-frequency-hz

70200000UL, //tx_synthesizer_frequency_hz *** adi,tx-synthesizer-frequency-hz

/* Rate & BW Control */

//{983040000, 245760000, 122880000, 61440000, 30720000, 30720000},//uint32_t rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies

//{983040000, 122880000, 122880000, 61440000, 30720000, 30720000},//uint32_t tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies

{884736000, 55296000, 18432000, 9216000, 4608000, 1152000},//uint32_t rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies

{884736000, 27648000, 9216000, 4608000, 2304000, 576000},//uint32_t tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies

1000000,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz

1000000,//rf_tx_bandwidth_hz *** adi,rf-tx-bandwidth-hz

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Then I have enabled all the half band filters like

RHB3 as decimate by 3 , RHB2 as decimate by 2,  RHB1 as decimate by 2, and  RFIR decimate  by 4(enabled the programmable FIR by setting phy->bypass_tx_fir = false; phy->bypass_rx_fir = false; in the AD9361_API.C file) .

This will give total division of 48 and therefore 27.648 div by 48 = 576 KHz clock which is same as data rate.

We have verified that this setting is done properly by reading the register 002 and 003 which read,

Reg 002 = EFh

Reg 003 = EFh

But we are not getting either the RF Transmitted signal (verified at Spectrum analyzer). When we are giving a signal of -50dBm at i/p of RX1, we are not able to receive any digital data (checked on chipscope analyzer).

Can anybody suggest what setting I need to do in the files to get the data rate of 576 KHz?

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