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Can not generate bitstream for FMcommS2 reference design with zedboard!?

Question asked by Jetmiri on Aug 5, 2014
Latest reply on Aug 6, 2014 by CsomI

I am using XPS 14.6 and I am trying to generate the bitstream for the model zedboard with FMCOMMs2 as it is given in

but I am receiving some errors. Is there problem with the reference ddesign or the problem is with my XPS version. Also I tryied to export to SDK it shows the same error. Is there any possibility to export to SDK from Vivado version in this link analogdevicesinc/hdl · GitHub but theri is no Vivado project file in there . I am using SDK 2013.2 and Vivado 2013.2.


The error is:

ERROR:EDK - axi_ad9122_0 (axi_ad9122) - 

INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_3.

ERROR:EDK:2951 -

   Unknown Tcl procedure ::hw_axi_ad9643_v1_00_a::run_coregen called

ERROR:EDK - axi_ad9643_0 (axi_ad9643) - 

INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_4.

ERROR:EDK:440 - platgen failed with errors!

make: *** [implementation/system.bmm] Error 2

 

Regards,

Jetmir


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