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AD9858 divide-by-2 operation

Question asked by tmain on Jul 30, 2014
Latest reply on Aug 4, 2014 by DSB

We use the AD9858 Direct Digital Synthesizer on our RF Controller board, which I inherited from a previous design engineer who has left the company.  I have a couple questions pertaining to its function that I was hoping you could provide some guidance.  See attached schematic page for circuit.


  1. We are performing a modification to the internal divide-by-2 circuit where we are applying ground to DVDD pins and power to a DGND pin.  I can’t find information explaining what exactly this is doing, but I believe the engineer received this configuration from ADI directly. Is this a valid configuration and could you explain how/why this works?
  2. The SYNCLK output is not a 3.3V signal when I measure it on my board.  What I see is a clock signal that is centered on 1.7V and is 300mV peak-to-peak.  Is the SYNCLK pin a CMOS output pin?  Should it be 0V to 3.3V?