I am looking at the ADV7842 and the audio outputs AP0 to AP5, SCLK, MCLK and i am trying to interface these to an FPGA. The logic level for my FPGA is 1.5V and the logic levels for the ADV7842 are 3.3V. I am trying to make the decision of using a level shifter or preferably using just a simple resistor network divider to get from one logic level to the other.
If i need to use level shifter i understand the design but i would prefer to use the resistor divider.
For the resistor divider could you let me know the minimum termination value that i could use? Or would you have a recommendation of resistor values to use for 3.3V and 1.5V. The I/Os on the FPGA side can sink some current but i would need to look at how much.
Thanks for your help.