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ADF4350 & simPLL

Question asked by TimW Employee on Sep 9, 2010
Latest reply on Sep 10, 2010 by icollins

How accurate is the lock time simulation results when using simPLL?  I noticed during a design that I couldn't get anything below 80us for a lock time, no matter what the loop filter was doing.  I was using a very high PFD to minimize the effect of the band select function, and should be under 1us for the band select.  I also noticed in the data sheet that we mentioned 50us lock times, so I'm guessing the limitation is in the software?

 

I guess the next question would be, what's about the fastest lock time one can expect using this device?  My application involves 1MHz frequency steps, using Frac mode, with a 10MHz ref and 10MHz PFD.

 

Thanks,

Tim

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