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relationship between internal PLL and MCLK input for AD1937 ?

Question asked by jtyx on Jul 28, 2014
Latest reply on Oct 13, 2014 by DaveThib

We have a project using ad1937 for analog audio play and record. the sclk for ADC and DAC is uncorrelated.
For the DAC,we use fpga provide the mclk(24.576Mhz),sclk(3.072Mhz),LRCK(48Khz).
For the ADC,we use fpga provide the sclk(3.072Mhz), LRCK(48Khz), and i want use the internal pll to generate the ADC's mclk.


But in our application scenarios, the ADC clock may unstable some time, so the LRCK provided to ad1937 is unstable too at that time.
I found when ALRCLK unstable, the DAC'S output is unstable too, But we can Confirm the MCLK / SCLK / LRCK for DAC is stable.
It's seem that the PLL unstabe state will have impack the DAC'S work state, is's right?

 

the register set is:

0x00  0xC8

0x01  0x01


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