This is regarding this PLL I am using for a university project. This PLL is part of a commercial transceiver and I am using Altera Cyclone2 fpga development board for programming. Currently I am unable to use the ADI recommended software & board for this purpose.
1. The fpga-pll interface has 3 wires - clock,data,and enable.
2. I tried integer-N mode with reference freq=10Mhz, N=25, fract=0, prescalar =4/5, R counter=1. Phase=1.
3. I did check DVDD, AVDD for PLL, and they look alright. Through MUXOUT, R output follows the input ref clock which is expected. But I don't get the correct waveform from the N counter output. This output is gnd with small variations (looks like highly attenuated high freq output). The final output of PLL is VDD (3.3V). Since I was not sure what value the charge pump must be given, I tried different CP values, enabling/disabling fundamental feedback and I also tried fract-N mode but all this resulted in the same problem.
The fpga keeps overwriting the register values after 1 cycle of the same is completed. I found that some bits are double buffered and the values in them wont be saved unless register 0 is written. If fpga completes write cycle multiple times then this should not be a problem,right?
I have fundamental knowledge of PLL. I would very much appreciate any help or guidance you are able to give me.