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FMCOMMS1 Change PLL2 Feedback Divider

Question asked by steve_c on Jul 25, 2014
Latest reply on Aug 21, 2014 by steve_c



I'm trying to know the process to change the , as indicated at Re: FMCOMMS1 - Changing ADC sampling frequency to 100MHz. By reading the AD9523-1's documentation, I see that counter A and counter B from PLL2's feedback divider are the important changes to make. However, when I try to change the value stored in pdata->pll2_ndiv_a_cnt and pdata->pll2_ndiv_b_cnt within AD9523.c, the ADC test freezes at

/* Wait until the new transfer is queued. */

    do {

   reg_val = Xil_In32(baddr + AXI_DMAC_REG_START_TRANSFER);
   xil_printf("The counters were not set correctly 1 :'(. %s\n\r", reg_val);// custom


Changing the values in AD9523_cfg.h doesn't appear to have any effect. I've also tried performing calibration and cynchronization directly after the changes, as recommended by the user manual, however the ADC test still hangs.