AnsweredAssumed Answered

Question about ADV7619 CP CORE BYPASSING

Question asked by Jane on Jul 25, 2014
Latest reply on Jul 25, 2014 by DaveD

Dear Sir,

It is mentioned in ADV7619 < Hardware User Guide UG-237> that: If the HDMI receiver receives video data above 2.25 GBps, data must be send directly to the video ouput formatter, bypassing the DPP and CP core, where it is output using two video buses running at half pixel clock frequency.

In <CP Core Bypassing> section, it is mentioned CP_COMPLETE_BYPASS_IN_HDMI_MODE, IO, Address 0xBF[0]

But in <ADV7619 REGISTER MAP DOCUMENTATION> , in the IO map register tables there is no 0XBF register.

When IO Map (0x98) register 0XBF[0] is set to 1, the display is freezing.

Would you please help to check and advise what is the correct method to bypass video data through CP core?

Thanks a lot in advance.

Best Regards!