1) For AD9625 is it mandatory to generate SYSREF from the sampling clock?
2) What will be the minimum & maximum frequency range of SYSREF ?
3) Can I able to use the power divider for getting the two SYSREF Clock ?
Yes, you are correct. The LMFC frequency should be faster than SYSREF by an integer multiple.
For example, LMFC could be 1x, 2x, 4x the SYSREF frequency such that the SYSREF rising edge always occurs on the LMFC clock boundaries. But the SYSREF frequency will be slower than LMFC.
1) The SYSREF signal is only needed for subclass 1 operation of the JESD204B interface for deterministic latency. The SYSREF signal does not need to be generated from the same source as the sample clock. However, since it should be source synchronous to the clock for sample accurate deterministic latency, the best choice is to have SYSREF generated from the same source as the sample clock.
2) SYSREF will need to be a harmonic of the LMFC frequency. This frequency will be established from the samples per frame and the frames per multi-frame parameter settings for JESD204B within the AD9625. The maximum frequency can not be faster than the LMFC. Since SYSREF could be a single pulse, there is not a minimum frequency.
3) The minimum differential voltage for SYSREF on the AD9625 is 250mVpp. The power can be split from the source, as long as the minimum Vswing is maintained at the SYSREF input to the AD9625.
In the 2nd point you have mentioned that
SYSREF will need to be a harmonic of the LMFC frequency.
That means SYSREF = Integer multiple of LMFC frequency.
But it should be LMFC frequency = Integer multiple of SYSREF.
Correct me if I got it wrong.
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