I was hoping someone had some advice on a random question. I have built the circuit in the "Circuit.jpg" attachment using the ADF4159 as the PLL chip. Initially I tested the circuit using a clear wave 1700MHz input as shown in the attached file and the PLL locked and displayed a clean 700MHz IF on the output. Next I changed the input to use a modulated 1700MHz as shown in the final attachment, now the PLL didn't lock and the IF output was constantly drifting in frequency and was very noisy. I realise the modulated signal is a much wider bandwidth signal but could someone explain why this causes the circuit to perform differently and maybe suggest on how to alter it so it can get lock again?